`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   22:58:28 11/22/2013
// Design Name:   Run_before_Decoder
// Module Name:   G:/Xilinx_Proj/H_264_test/RunBefore_decoder_test.v
// Project Name:  H_264_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Run_before_Decoder
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module RunBefore_decoder_test;

	// Inputs
	reg [63:0] Code;
	reg Clk;
	reg Rst;
	reg Sig_start;
	reg [4:0] TotalCoeff;
	reg [3:0] TotalZero;
	reg [8:0] Level_0;
	reg [8:0] Level_1;
	reg [8:0] Level_2;
	reg [8:0] Level_3;
	reg [8:0] Level_4;
	reg [8:0] Level_5;
	reg [8:0] Level_6;
	reg [8:0] Level_7;
	reg [8:0] Level_8;
	reg [8:0] Level_9;
	reg [8:0] Level_10;
	reg [8:0] Level_11;
	reg [8:0] Level_12;
	reg [8:0] Level_13;
	reg [8:0] Level_14;
	reg [8:0] Level_15;

	// Outputs
	wire Sig_done;
	wire [7:0] RunBefore_code_length;
	wire [8:0] Level_0_de;
	wire [8:0] Level_1_de;
	wire [8:0] Level_2_de;
	wire [8:0] Level_3_de;
	wire [8:0] Level_4_de;
	wire [8:0] Level_5_de;
	wire [8:0] Level_6_de;
	wire [8:0] Level_7_de;
	wire [8:0] Level_8_de;
	wire [8:0] Level_9_de;
	wire [8:0] Level_10_de;
	wire [8:0] Level_11_de;
	wire [8:0] Level_12_de;
	wire [8:0] Level_13_de;
	wire [8:0] Level_14_de;
	wire [8:0] Level_15_de;
	wire [3:0] level_cnt_t;
	wire [3:0] CodeLength;
	reg [5:0]cnt;
	// Instantiate the Unit Under Test (UUT)
	run_before_decoder uut (
		.Code(Code), 
		.Clk(Clk), 
		.Rst(Rst), 
		.Sig_start(Sig_start), 
		.Sig_done(Sig_done), 
		.TotalCoeff(TotalCoeff), 
		.TotalZero(TotalZero), 
		.RunBefore_code_length(RunBefore_code_length), 
		.Level_0(Level_0), 
		.Level_1(Level_1), 
		.Level_2(Level_2), 
		.Level_3(Level_3), 
		.Level_4(Level_4), 
		.Level_5(Level_5), 
		.Level_6(Level_6), 
		.Level_7(Level_7), 
		.Level_8(Level_8), 
		.Level_9(Level_9), 
		.Level_10(Level_10), 
		.Level_11(Level_11), 
		.Level_12(Level_12), 
		.Level_13(Level_13), 
		.Level_14(Level_14), 
		.Level_15(Level_15), 
		.Level_0_de(Level_0_de), 
		.Level_1_de(Level_1_de), 
		.Level_2_de(Level_2_de), 
		.Level_3_de(Level_3_de), 
		.Level_4_de(Level_4_de), 
		.Level_5_de(Level_5_de), 
		.Level_6_de(Level_6_de), 
		.Level_7_de(Level_7_de), 
		.Level_8_de(Level_8_de), 
		.Level_9_de(Level_9_de), 
		.Level_10_de(Level_10_de), 
		.Level_11_de(Level_11_de), 
		.Level_12_de(Level_12_de), 
		.Level_13_de(Level_13_de), 
		.Level_14_de(Level_14_de), 
		.Level_15_de(Level_15_de),
		.level_cnt_t(level_cnt_t),
		.CodeLength(CodeLength)
	);

	initial begin
		// Initialize Inputs
		Code = 0;
		Clk = 0;
		Rst = 0;
		Sig_start = 0;
		TotalCoeff = 0;
		TotalZero = 0;
		Level_0 = 0;
		Level_1 = 0;
		Level_2 = 0;
		Level_3 = 0;
		Level_4 = 0;
		Level_5 = 0;
		Level_6 = 0;
		Level_7 = 0;
		Level_8 = 0;
		Level_9 = 0;
		Level_10 = 0;
		Level_11 = 0;
		Level_12 = 0;
		Level_13 = 0;
		Level_14 = 0;
		Level_15 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        cnt = 0;  
		// Add stimulus here
		#50 Rst = 0;
		#50 Rst = 1;
		// Add stimulus here

	end
      
always #20 Clk=~Clk;
always @(posedge Clk or negedge Rst) begin
		if(!Rst) begin
			cnt <= 0;
		end
		else begin
			case(cnt)
			0:begin
				Code <= 64'b101101;
				TotalCoeff <= 5;
				TotalZero <= 3;
				Sig_start <= 1;
				Level_0 <= 1;
				Level_1 <= -1;
				Level_2 <= -1;
				Level_3 <= 1;
				Level_4 <= 3;
				Level_5 <= 0;
				Level_6 <= 0;
				Level_7 <= 0;
				Level_8 <= 0;
				Level_9 <= 0;
				Level_10 <= 0;
				Level_11 <= 0;
				Level_12 <= 0;
				Level_13 <= 0;
				Level_14 <= 0;
				Level_15 <= 0;
				cnt <= 1;
			end
			1:begin
				Sig_start <= 0;
				if(Sig_done==1'b1)begin
					cnt<=2;
				end
				else begin
					cnt<=1;
				end
			end
			2:begin
				Code <= 64'b00;
				TotalCoeff <= 5;
				TotalZero <= 2;
				Sig_start <= 1;
				Level_0 <= -1;
				Level_1 <= -3;
				Level_2 <= 3;
				Level_3 <= 4;
				Level_4 <= -2;
				Level_5 <= 0;
				Level_6 <= 0;
				Level_7 <= 0;
				Level_8 <= 0;
				Level_9 <= 0;
				Level_10 <= 0;
				Level_11 <= 0;
				Level_12 <= 0;
				Level_13 <= 0;
				Level_14 <= 0;
				Level_15 <= 0;
				cnt <= 3;
			end
			3:begin
				Sig_start <= 0;
				if(Sig_done==1'b1)begin
					cnt<=4;
				end
				else begin
					cnt<=3;
				end
			end
			4:begin
				Code <= 64'b111010;
				TotalCoeff <= 5;
				TotalZero <= 5;
				Sig_start <= 1;
				Level_0 <= 1;
				Level_1 <= -1;
				Level_2 <= 2;
				Level_3 <= 3;
				Level_4 <= 5;
				Level_5 <= 0;
				Level_6 <= 0;
				Level_7 <= 0;
				Level_8 <= 0;
				Level_9 <= 0;
				Level_10 <= 0;
				Level_11 <= 0;
				Level_12 <= 0;
				Level_13 <= 0;
				Level_14 <= 0;
				Level_15 <= 0;
				cnt <= 5;
			end
			5:begin
				Sig_start <= 0;
				if(Sig_done==1'b1)begin
					cnt<=6;
				end
				else begin
					cnt<=5;
				end
			end
			6:begin
				cnt<=6;
			end
			endcase
		end
end
		
endmodule

